1. Technical Field of the Invention
The invention relates generally to communication systems; and, more particularly, it relates to employing a trellis when performing iterative decoding processing of coded signals of such communication systems.
2. Description of Related Art
Data communication systems have been under continual development for many years. One such type of communication system that continues to be of significant interest is that which employs iterative error correction codes. Some examples of iterative correction codes include LDPC (Low Density Parity Check) codes and turbo codes. Communications systems with iterative codes are often able to achieve lower BER (Bit Error Rate) than alternative codes for a given SNR (Signal to Noise Ratio).
A continual and primary directive in this area of development has been to try continually to lower the SNR required to achieve a given BER within a communication system. The ideal goal has been to try to reach Shannon's limit in a communication channel. Shannon's limit may be viewed as being the data rate to be used in a communication channel, having a particular SNR, that achieves error free transmission through the communication channel. In other words, the Shannon limit is the theoretical bound for channel capacity for a given modulation and code rate.
Looking at error correcting LDPC codes, various types of LDPC codes have been shown to provide for excellent decoding performance that can approach the Shannon limit in some cases. For example, some LDPC decoders have been shown to come within 0.3 dB (decibels) from the theoretical Shannon limit. While this example was achieved using an irregular LDPC code of a length of one million, it nevertheless demonstrates the very promising application of LDPC codes within communication systems.
Within LDPC and other types of communication systems, a trellis is oftentimes employed to perform the detection of a coded signal that undergoes error corrective decoding. Moreover, sometimes the coded signal includes parity (e.g., one or more redundancy bits) as well and the trellis needs to be designed to accommodate this parity. In prior art systems, both the parity trellis and the non-parity trellis need to be implemented in hardware (which can be storing information corresponding to the trellis in memory) so that both the signal can employ the parity trellis at some times, and the non-parity trellis at other times when decoding the coded signal. Prior art approaches to representing these two trellises in hardware (e.g. in memory) are generally very inefficient, in that, the states and connectivity between each of the appropriate states is stored separately for both of the parity trellis and the non-parity trellis. In other words, in such a situation, there must be sufficient hardware (e.g. memory) provisioned to represent two totally distinct and separate trellises (i.e., the parity trellis and the non-parity trellis).
There exists a need in the art for a more efficient means by which more than one trellis can be represented in hardware (e.g. memory) for use in decoding different types of coded signals (e.g., those having parity and those not having parity).